Seminars

April 13, 2021: Dr. Dang Nam Khanh (VNU Univ. Eng. Tech.), Fault-tolerance through-silicon-via for 3-D integrated circuits

Through-Silicon-Via (TSV) is considered as the nearfuture solution to realize low-power and highperformance 3D-Integrated Circuits (3D-ICs) and 3DNetwork-on-Chips (3D-NoCs). However, imperfection in TSV-based IC manufacture has been one of the most critical challenge for realizing this technology. Moreover, the lifetime reliability issue of TSV due to its fault sensitivity and the high operating temperature of 3D-ICs, which also accelerates the fault-rate, is one of the most critical challenges. In this presentation, we will discuss the method to detect, diagnose and recover the TSV defects.

Speaker: Dr. Dang Nam Khanh, VNU Univ. Eng. Tech.

Time: 15:30, Tuesday, April 13, 2021

Venue: G2-315, 144 Xuan Thuy, Cau Giay, Hanoi

Khanh N. Dang received his Ph.D. degree from The University of Aizu, Japan in 2017. Since 2017, he has been a lecturer at VNU Key Laboratory for Smart Integrated Systems, Vietnam National University Hanoi (VNU), Hanoi Vietnam. Dr. He is/was a visiting researcher at the University of Aizu in 2019 and 2020-2021. His research interests include System-on-Chips/Network-on-Chips, 3D-ICs, neuromorphic computing, machine learning, and fault-tolerant systems.

SAME CATEGORY

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